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Two-bit charge trap nonvolatile memory device and methods of operating and fabricating the same

机译:两位电荷陷阱非易失性存储器件及其操作和制造方法

摘要

Two-bit programmable nonvolatile memory devices and methods of operating and fabricating the same are provided. The device comprises a plurality of device isolation layers, a plurality of word lines crossing over the device isolation layers, and a multiple insulation layer intervened between the word line and the active region. The multiple insulation layer includes a charge trap insulation layer. A source/drain region is formed at each region defined by adjacent word lines and the adjacent device isolation layers. The source/drain regions have the same surface area. A write operation of the device comprises applying a first level voltage, a ground voltage, and a write voltage to one bit line, another bit line, and a selected word line, thereby writing data into a charge trap insulation layer. By changing the voltages applied to the bit lines, 2 bits may be stored in one memory cell.
机译:提供了一种两位可编程非易失性存储器件及其操作和制造方法。所述器件包括多个器件隔离层,在所述器件隔离层上交叉的多条字线以及介于所述字线与所述有源区之间的多个绝缘层。多层绝缘层包括电荷陷阱绝缘层。源极/漏极区形成在由相邻的字线和相邻的器件隔离层限定的每个区域处。源极/漏极区域具有相同的表面积。器件的写操作包括将第一电平电压,地电压和写电压施加到一条位线,另一条位线和选择的字线,从而将数据写到电荷陷阱绝缘层中。通过改变施加到位线的电压,可以将2个位存储在一个存储单元中。

著录项

  • 公开/公告号US2006007745A1

    专利类型

  • 公开/公告日2006-01-12

    原文格式PDF

  • 申请/专利权人 JEONG-HYUK CHOI;

    申请/专利号US20050229256

  • 发明设计人 JEONG-HYUK CHOI;

    申请日2005-09-16

  • 分类号G11C11/34;

  • 国家 US

  • 入库时间 2022-08-21 21:46:08

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