首页> 外国专利> Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

Semiconductor Device and Method of Forming Stacked Vias Within Interconnect Structure for FO-WLCSP

机译:半导体器件和在互连结构内形成用于FO-WLCSP的堆叠通孔的方法

摘要

A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over the encapsulant and semiconductor die. First vias are formed through the first insulating layer to expose contact pads of the semiconductor die. A first conductive layer is formed over the first insulating layer and into the first vias to electrically connect to the contact pads of the semiconductor die. A second insulating layer is formed over the first insulating layer and first conductive layer. Second vias are formed through the second insulating layer by laser direct ablation and aligned or offset with the first vias to expose the first conductive layer. A second conductive layer is formed over the second insulating layer and into the second vias. Conductive vias can be formed through the encapsulant.
机译:半导体器件具有安装在载体上的半导体管芯。密封剂沉积在半导体管芯和载体上方。载体被移除。在密封剂和半导体管芯上方形成第一绝缘层。形成穿过第一绝缘层的第一通孔以暴露半导体管芯的接触垫。在第一绝缘层上方并在第一通孔中形成第一导电层,以电连接到半导体管芯的接触垫。在第一绝缘层和第一导电层上方形成第二绝缘层。通过激光直接烧蚀形成穿过第二绝缘层的第二通孔,并且与第一通孔对准或偏移以暴露第一导电层。在第二绝缘层上方并在第二通孔中形成第二导电层。可以通过密封剂形成导电通孔。

著录项

  • 公开/公告号US2016276239A1

    专利类型

  • 公开/公告日2016-09-22

    原文格式PDF

  • 申请/专利权人 STATS CHIPPAC PTE. LTD.;

    申请/专利号US201615169261

  • 发明设计人 YAOJIAN LIN;RUI HUANG;KANG CHEN;YU GU;

    申请日2016-05-31

  • 分类号H01L23/31;H01L25/065;H01L25;H01L23/538;H01L23;H01L23/29;H01L23/522;H01L23/498;

  • 国家 US

  • 入库时间 2022-08-21 14:37:29

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