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A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance

机译：系统内部模内互连和器件变化对电路性能影响建模的方法论

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Vikas Mehrotra; Shiou Lin Sam; Duane Boning; Anantha Chandrakasan; Anantha Ch; Rakesh Vallishayee; Sani Nassif;
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年度 2000
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1. On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology [J] . B. P. Harish, Navakanta Bhat, Mahesh B. Patil IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2007,第期

机译：关于使用响应面方法对过程变化对电路延迟性能的影响进行建模的通用框架
2. Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing [J] . Munkang Choi, Milor L. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2006,第7期

机译：纳米级半导体制造中确定性晶粒内变异对电路性能的影响
3. Interconnects for Novel State Variables: Performance Modeling and Device and Circuit Implications [J] . Rakheja S., Naeemi A. Electron Devices, IEEE Transactions on . 2010,第10期

机译：新型状态变量的互连：性能建模以及设备和电路的含义
4. A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance [C] . Vikas Mehrotra, Shiou Lin Sam, Duane Boning, Conference on Design automation . 2000

机译：一种用于建模系统内芯片内部互连和器件变化对电路性能的影响的方法
5. Modeling the effects of device and interconnect process variation on high-speed circuit performance. [D] . Khazamipour, Ali Asghar. 2003

机译：建模器件和互连工艺变化对高速电路性能的影响。
6. PNAS Plus: Modeling integrated photovoltaic–electrochemical devices using steady-state equivalent circuits [O] . Mark T. Winkler, Casandra R. Cox, Daniel G. Nocera, 2013

机译：PNAS Plus：使用稳态等效电路为集成的光伏电化学设备建模
7. On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology [O] . Harish BP, Bhat Navakanta, Patil Mahesh B 2007

机译：关于使用响应面方法对过程变化对电路延迟性能的影响进行建模的通用框架

A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance

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