Bias Temperature Instability Effects in Devices with Fully-Silicided Gate Stacks, Strained-Si and Multiple-Gate Architectures

摘要

ContentsChapter I: Introduction23I.1. CMOS Device Scaling23I.2. Objectives of the thesis29I.3. Structure of the thesis30Chapter II: State-of-the-Art Experimental Techniques30Chapter III: Reliability of Devices with Fully Silicided Gate Stacks30Chapter IV: Reliability of Strained-Si Devices30Chapter V: Reliability of Devices with Multiple-Gate Architectures31Chapter VI: Conclusions and Future Work31Bibliography32Chapter II: State-of-the-Art Experimental Techniques37II.1 Introduction37II. 2. Bias Temperature Instability37II.2.1. NBTI models38II.2.1.1. Reaction–Diffusion (R–D) model38II.2.1.2. Disorder-Controlled Kinetics model39II.2.2. Activation energy and time dependence41II.2.3. Interface traps and oxide charges43II.2.4. NBTI recovery46II.2.5. Nitrogen and fluorine47II.2.6. Wafer orientation48II.2.7. BTI measurement set-up48II. 3. Complementary Electrical Characterization Techniques50II.3.1. The conventional Charge Pumping (CP)50II.3.2. Conventional frequency sweep52II.3.3. Variable Tcharge-Tdischarge-Charge Pumping: VT2CP52II.3.4. Stress-Induced Leakage Current (SILC)55II.3.5. Low-frequency Noise58II.3.5.1 McWhorter's (DN) Surface Modulation Noise Mechanism60II.3.5.2. Hooge's (Dm) Mobility Fluctuation Mechanism61II.3.6. Time Dependent Dielectric Breakdown (TDDB)62II.3.6.1. Constant current stress (CCS)63II.3.6.2. Constant voltage stress (CVS)63II.3.6.3. TDDB analysis: the Weibull distribution64II. 4. Conclusions67Bibliography68Chapter III: Reliability of Devices with Fully Silicided Gate Stacks77III.1. Introduction77III.2. FUSI Process Flow79III.2.1. Ni silicide phase formation and effective work function79III.2.2. Scalability of Ni FUSI gate processes and device implementation82III.2.3. Dual work function phase controlled Ni FUSI CMOSintegration scheme86III.2.4. Summary89III. 3. Reliability Studies90III.3.1. Motivation90III.3.2.Device Processing Details and Experimental Techniques90III.3.3. Experimental Results91III.3.3.1. Effect of Gate Electrode on NBTI91III.3.3.2. Effect o f Back-End-of-Line Thermal Budget on BTI96III.3.3.3.Effects of Nitridation Conditions on BTI99III.3.3.4. Observations on the scalability of the BTI behaviour in sub-1nm EOT dielectrics109III. 4. Conclusions111Bibliography113Chapter IV: Reliability of Strained-Si Devices119IV. 1. Introduction119IV. 2. Transport Enhancement121IV.2.1. Electron mobility121IV.2.2. Hole mobility122IV.2.3. Piezoresistance coefficients123IV.2.4. Dangling bonds126IV. 3. Strain introduction techniques127IV.3.1. Stress-strain relationship127IV.3.2. Global strain substrates127IV.3.3. SiGe and Si:C Source/Drain130IV.3.4. Contact-Etch Stop Layers (CESL)133IV.3.5. Stress Memorization Technique (SMT)136IV. 4. Reliability Studies137IV.4.1. Motivation137IV.4.2. Device Processing Details and Experimental Techniques138IV.4.3. Experimental Results140IV.4.3.1. NBTI Characterization140IV.4.3.2. Charge pumping and noise measurements145IV.4.3.3. Impact of strain on carrier mobility in the vertical direction148IV.4.3.4. Electron Spin Resonance (ESR) measurements150IV.4.3.5. Discussion151IV. 5. Conclusions153Bibliography154Chapter V: Reliability of Devices with Multiple-Gate Architectures163V.1. Introduction163V.2. Types of Multiple-Gate Devices164V.2.1. Planar Double-Gate devices165V.2.2. Tri-Gate devices165V.2.3. Vertical Double-Gate devices165V.2.4. W-Gate devices165V.2.5. Gate-All-Around (GAA) 165V.2.6. P-Gate devices166V.2.7. Summary167V.3. Reliability Studies168V.3.1. Motivation168V.3.2. Device Processing Details and Experimental Techniques169V.3.2.1. Devices used in Section V.3.3.1:(Effects of Corner Rounding on TDDB)169V.3.2.2. Devices used in Section V.3.3.2:(Effects of Fluorine Passivation on BTI)169V.3.2.3. Devices used in Section V.3.3.3: (Effects of Nitridation Techniques on BTI)170V.3.3. Experimental Results171V.3.3.1. Effects of Corner Rounding on TDDB171Sub-Section V.3.3.1.A. Devices without corner rounding173Sub-Section V.3.3.1.B. Devices with corner rounding177V.3.3.2. Effects of Fluorine Passivation on BTI180V.3.3.3. Effects of Nitridation Techniques on BTI189V.4. Conclusions195Bibliography196Chapter VI: Summary, Conclusions and Future Work203VI.1. Summary203VI.2. Main conclusions203VI.2.1. Reliability of Devices with Fully Silicided Gate Stacks203VI.2.2. Reliability of Strained-Si Devices205VI.2.3. Reliability of Devices with Multiple-Gate Architectures206VI.3. Future work208VI.3.1. Reliability of Devices with Fully Silicided Gate Stacks208VI.3.2. Reliability of Strained-Si Devices208VI.3.3. Reliability of Devices with Multiple-Gate Architectures208Curriculum Vitae209