Data Compression for Maskless Lithography Systems: Architecture, Algorithms and Implementation

摘要

Future lithography systems must produce more dense microchips with smaller feature sizes, while maintaining throughput comparable to today's optical lithography systems. This places stringent data-handling requirements on the design of any maskless lithography system. Today's optical lithography systems transfer one layer of data from the mask to the entire wafer in about sixty seconds. To achieve a similar throughput for a direct-write maskless lithography system with a pixel size of 22 nm, data rates of about 12 Tb/s are required. In this thesis, we propose a datapath architecture for delivering such a data rate to a parallel array of writers. Our proposed system achieves this data rate contingent on two assumptions: consistent 10 to 1 compression of lithography data, and implementation of real-time hardware decoder, fabricated on a microchip together with a massively parallel array of lithography writers, capable of decoding 12 Tb/s of data. To address the compression efficiency problem, we explore a number of existing binary and gray-pixel lossless compression algorithms and apply them to a variety of microchip layers of typical circuits such as memory and control. The compression efficiency of various compression algorithms have been characterized on a variety of layouts sampled from many industry sources. Overall, we have found that compression efficiency varies significantly from design to design, from layer to layer, and even within parts of the same layer. The decoder for any chosen compression scheme must be replicated in hardware tens of thousands of times, to achieve the 12 Tb/s decoding rate. We explore the tradeoff between the compression ratio, and decoder buffer size for C4. We show that for a fixed buffer size, C4 achieves a significantly higher compression ratio than those of existing compression algorithms. We also present a detailed functional block diagram of the C4 decoding algorithm as a first step towards a hardware realization.