Full-chip characterization of compression algorithms for direct-write maskless lithography systems

摘要

Future lithography systems must produce more dense micro-nchips with smaller feature sizes while maintaining throughput compa-nrable to today’s optical lithography systems. This places stringent data-nhandling requirements of up to 12 Tb/s on the design of any masklessnlithography system. In past work, we have developed data-path architec-ntures for such throughput and shown that lossless compression algo-nrithms play a key role in such systems. We currently investigate theneffectiveness of the Block C4 lossless layout compression algorithm innincreasing throughput of direct-write maskless lithography systems. Innparticular, we characterize the compression efficiency of Block C4 onn1024u00011024 blocks of select layers of two 65-nm chips: a state-of-the-artnmicroprocessor chip and a low-density parity code chip used commonlynin wireless communication applications. Overall, we have found thatncompression efficiency varies significantly from design to design, fromnlayer to layer, and even within parts of the same layer. We propose annumber of ways to cope with the variation of compression ratios within anlayer and characterize the way each method affects the overall wafernlayer throughput