Scheduling tests for VLSI systems under power constraints

摘要

This paper considers the problem of testing VLSI integratedncircuits in minimum time without exceeding their power ratings duringntest. We use a resource graph formulation for the test problem. Thensolution requires finding a power-constrained schedule of tests. Twonformulations of this problem are given as follows: (1) scheduling equalnlength tests with power constraints and (2) scheduling unequal lengthntests with power constraints. Optimum solutions are obtained for bothnformulations. Algorithms consist of four basic steps. First, a testncompatibility graph is constructed from the resource graph. Second, thentest compatibility graph is used to identify a complete set of timencompatible tests with power dissipation information associated with eachntest. Third, from the set of compatible tests, lists of power compatiblentests are extracted. Finally, a minimum cover table approach is used tonfind an optimum schedule of power compatible tests