Test Scheduling of Modular System-on-Chip under Capture Power Constraint

摘要

Testing of an System-on-Chip (SoC) often produces larger switching activity than the functional mode. This causes power droop due to which a good chip mayfail the test that leads to yield loss. The problem becomes severe when multiple cores in an SoC, scheduled together, apply test vectors and capture test response simultaneously. i.e., when capture cycle coincide. This paper proposes a methodology to schedule cores under capture power constraint. The proposed methodology minimizes test time under capture power constraint.