REDUCING TEST TIME AND SYSTEM-ON-CHIP (SOC) AREA REDUCTION USING SIMULTANEOUS CLOCK CAPTURE BASED ON VOLTAGE SENSOR INPUT

摘要

A method and apparatus for testing an electronic component is provided. The method begins when a design-for-test (DFT) mode is entered and at least one sensor is enabled. Sensor results are monitored and determine the number of cores or capture domains that may be tested simultaneously. The sensors include a voltage and temperature sensor, and either or both sensors may be enabled during testing. Maximum and minimum voltage levels for each capture domain determine at what value a voltage drop occurs. The number of cores selected minimizes a voltage drop across the electronic component. Maximum and minimum temperatures across the multiple cores of the electronic component determine the number of clocks that may be operated simultaneously during testing. An apparatus includes an electronic device to be tested, test sensors on the electronic device, and an interface to a test fixture.