A Genetic Algorithm Based Approach for System-on-Chip test Scheduling using Dual Speed TAM with Power Constraint

摘要

Increasing complexity of System-on-Chip (SOC) has encouraged the engineers to design versatile automated test equipments (ATE) that can drive simultaneously different data channels at different data rates so that overall test cost can be reduced. Devices like Agilent 93000 series tester and Tiger system from Teradyne provide such flexibility to drive different channels at different data rates. Number of tester channels with higher data rate is limited due to different constraints like power rating of the SOCs, limitation of scan frequency, complexity of ATE etc. Hence proper utilization of the tester channels to reduce test time and thereby test cost is important. In this paper we provide a Genetic algorithm based approach for SOC-level TAM architecture optimization that minimizes testing time considering two different data rates for ATE channels. Our approach achieves better results than those reported in the literature. Experimental results show that the maximum improvement of 40.99% in testing time can be achieved. We have also addressed the issue of power constrained testing.