Analog/RF performance analysis of inner gate engineered junctionless Si nanotube

摘要

This paper investigates the analog/RF performance of inner gate engineered junctionless silicon nanotube (JLSiNT) FETs. We demonstrate that the RF performance of symmetric drain/source DS-JLSiNT-FETs (inner gate extended from one end of nanotube to other end covering both drain and source region) gets improved when the inner gate of nanotube (NT) covers only either drain and channel regions (D-JLSiNT-FETs) or source and channel regions (S-JLSiNT-FETs) because of reduced total gate capacitance. The improvement in cut-off frequency (f_T) in D-JLSiNT-FETs is ～45% whereas in S-JLSiNT-FETs is ～23% as compare to DS-JLSiNT-FETs. However, the percentage improvement in maximum oscillation frequency (f_(MAX)) is more in S-JLSiNT-FETs. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity (EI) is reduced resulting in degraded intrinsic gain (A_V). However, the deterioration in A_V is almost minimal (～0.4 dB) for D-JLSiNT-FETs as compared to DS-JLSiNT-FETs but the deterioration in A_V is aggravated to ～22 dB for S-JLSiNT-FETs. The up scaling of Source/Drain extension length improves the performance of D-JLSiNT-FETs but degrade the performance of S-JLSiNT-FETs when compared to DS-JLSiNT-FETs. The improvement in f_T and f_(MAX) in D-JLSiNT-FETs as well as in S-JLSiNT-FETs are pronounced with outer gate length scaling when compared to DS-JLSiNT-FETs.