Analog/RF performance analysis of channel engineered high-K gate-stack based junctionless Trigate-FinFET

摘要

In this paper, the effect of channel parameters like channel thickness (T_(Si)) and channel length (L_g) on the analog/RF performance of high-K gate-stack based junctionless Trigate-FinFET (JLT-FinFET) have been studied using TCAD mixed-mode Sentaurus device simulator. It is observed that use of high-K gate dielectric deteriorates the analog/RF performance of the gate-stack based JLT-FinFET. The variation of change in analog/RF FOMs (△FOM = FOM_(K=3.9) - FOM_(K-40)) with respect to channel parameters have been focused throughout this study. It is observed that the deterioration in intrinsic dc gain (△Av = (Av_((K-3.9)) - A_V_((K=40)))) with high-K gate dielectrics aggravates with scaling down of T_(Si) (from 2.31 dB at T_(Si) = 12 nm to 5.2 dB at T_(Si) = 6 nm) but increases marginally with scaling down of L_g (△A_V = 7.6 dB at L_g = 30 nm and △A_V = 8.7 dB at L_g = 15 nm). However, the deterioration in maximum oscillation frequency (△f_(MAX)) and cut-off frequency (△f_T) are almost negligible. Moreover, it is also observed that the deterioration in analog/RF FOMs due to high-K gate dielectrics can be reduced by upscaling of interfacial layer thickness (T_1). Consequently, higher T_1 value can be convenient in designing of high-K gate-stack based junctionless Trigate-FinFET at lower T_(Si) for analog/RF applications.