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首页> 外文期刊>Journal of Computational Electronics >A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor
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A surface-potential based drain current model for short-channel symmetric double-gate junctionless transistor

机译:基于表面电势的短沟道对称双栅无结晶体管的漏极电流模型

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摘要

Junctionless transistors, which do not have any pn junction in the source-channel-drain path have become an attractive candidate in sub-20 nm regime. They have homogeneous and uniform doping in source-channel-drain region. Despite some similarities with conventional MOSFETs, the charge-potential relationship is quite different in a junctionless transistor, due to its different operational principle. In this report, models for potential and drain current are formulated for shorter channel symmetric double-gate junctionless transistor (DGJLT). The potential model is derived from two dimensional Poisson's equation using "variable separation technique". The developed model captures the physics in all regions of device operation i.e., depletion to accumulation region without any fitting parameter. The model is valid for a range of channel doping concentrations, channel thickness and channel length. Threshold voltage and drain-induced barrier lowering values are extracted from the potential model. The model is in good agreement with professional TCAD simulation results.
机译:在源-沟道-漏极路径中没有任何pn结的无结晶体管已成为20纳米以下制程的诱人候选。它们在源-沟道-漏区中具有均匀且均匀的掺杂。尽管与常规MOSFET有一些相似之处,但由于无结晶体管的工作原理不同,其电荷电势关系也有很大不同。在本报告中,针对较短的沟道对称双栅极无结晶体管(DGJLT)制定了电势和漏极电流模型。势模型是使用“变量分离技术”从二维泊松方程导出的。所开发的模型捕获了设备操作所有区域中的物理特性,即没有任何拟合参数就耗尽了累积区域。该模型对一定范围的沟道掺杂浓度,沟道厚度和沟道长度有效。从电势模型中提取阈值电压和漏极引起的势垒降低值。该模型与专业的TCAD仿真结果非常吻合。

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