Optimizing the Gate-to-Drift Overlap Length of Lateral Double Diffused Metal-Oxide-Semiconductor Field Effect Transistor Devices to Improve Hot-Carrier Device Lifetime

摘要

In this study, the gate-to-drift overlap length of lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOST) devices is optimized in order to increase their hot-carrier lifetime. LDMOST devices with drift regions are fabricated using a 0.25 μm complementary metal-oxide-semiconductor (CMOS) process. The gate-to-drift overlap lengths in the drift region are 0.1, 0.4, 0.8, and 1.1 μm, respectively. The breakdown voltages, on-resistances and hot-carrier degradations of the fabricated LDMOST devices are characterized. The LDMOST device with a gate-to-drift overlap length of 0.4 μm showed the longest on-resistance hot-carrier lifetime of 9.34 x 10~5 s, along with a breakdown voltage of 22V and an on-resistance of 23 m浮m~2.