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A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

机译:新型双材料双栅(DMDG)纳米SOI MOSFET二维分析建模与仿真

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摘要

In this paper, we present the unique features exhibited by a modified asymmetrical double-gate (DG) silicon-on-insulator (SOI) MOSFET. The proposed structure is similar to that of the asymmetrical DG SOI MOSFET with the exception that the front gate consists of two materials. The resulting modified structure, i.e., a dual-material double-gate (DMDG) SOI MOSFET, exhibits significantly reduced short-channel effects (SCEs) when compared with the DG SOI MOSFET. SCEs in this structure have been studied by developing an analytical model. The model includes the calculation of the surface potential, electric field, threshold voltage, and drain-induced barrier lowering. A model for the drain current, transconductance, drain conductance, and voltage gain is also discussed. It is seen that SCEs in this structure are suppressed because of the perceivable step in the surface-potential profile, which screens the drain potential. We further demonstrate that the proposed DMDG structure provides a simultaneous increase in the transconductance and a decrease in the drain conductance when compared with the DG structure. The results predicted by the model are compared with those obtained by two-dimensional simulation to verify the accuracy of the proposed analytical model.
机译:在本文中,我们介绍了一种改进的不对称双栅极(DG)绝缘体上硅(SOI)MOSFET所展现的独特功能。除了前栅极由两种材料组成外,该结构与非对称DG SOI MOSFET的结构相似。与DG SOI MOSFET相比,改进后的结构,即双材料双栅极(DMDG)SOI MOSFET表现出显着降低的短沟道效应(SCE)。已经通过建立分析模型研究了这种结构的SCE。该模型包括表面电势,电场,阈值电压和漏极引起的势垒降低的计算。还讨论了漏极电流,跨导,漏极电导和电压增益的模型。可以看出,由于表面电势分布中可察觉的台阶,该结构中的SCE被抑制,从而屏蔽了漏极电势。我们进一步证明,与DG结构相比,建议的DMDG结构提供了跨导的同时增加和漏极电导的降低。将模型预测的结果与二维模拟获得的结果进行比较,以验证所提出的分析模型的准确性。

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