Modeling and optimal design of nanoscale double-gate CMOS devices and technology.

摘要

This dissertation seeks to model underlying physical effects, and gain insights into the optimal design of nanoscale Double-Gate (DG) MOSFETs, particularly the quasi-planar FinFET structure. Our work includes design of a novel FinFET-based device structure (scalable ITFET), evaluation of the suitability of high-k gate dielectrics for nanoscale FinFETs, a model for parasitic fringe capacitance in DG FinFETs, and insights on optimal source/drain (S/D) process design and carrier mobility in short-channel FinFETs.;The ITFET is a recently proposed hybrid device which consists of a FinFET and planar FD/SOI MOSFET combined into a single device with a common gate. The advantage of the ITFET is that it enhances the on-state current per pitch by ∼100%; its disadvantage is poor scalability. We propose a novel ITFET design which is scalable to near the end of the ITRS roadmap while still giving reasonable enhancement in on-state current, Ion (∼20-35%).;We perform a realistic assessment of the performance and scalability advantage of high-k dielectrics in FinFET-CMOS technology. Our results indicate that a high-k dielectric actually undermines circuit performance while giving limited improvement in scalability. We conclude that high-k gate dielectrics are not suitable for nanoscale FinFETs.;We present a physical model for fringe capacitance (Cf) in DG MOSFETs with non-abrupt S/D junctions. We model Cf in terms of the device structure and short-channel effects (SCEs). The model is implemented in our physical/process based compact model, UFDG, and will enable quasi-predictive device/circuit simulations.;In undoped UTB FinFETs, the lateral S/D doping profile, NSD(y), defines the tradeoff between SCEs and parasitic resistance, RS/D, via gate-source/drain underlap. We demonstrate a reverse-engineering methodology to extract NSD(y) from FinFET CG-V GS and IDS-VGS data. The extracted NSD(y) is then used to redesign the S/D process to effect a better tradeoff between SCEs and RS/D.;Finally, we discuss the degradation of mobility in short-channel FinFETs possibly due to S/D defects/dopants. We explore possible causes of the phenomenon and make device processing suggestions to help mitigate the effect.