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3.3 Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device

机译：3.3双栅极器件的纳米级CmOs电路漏电功率降低

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Keunwoo Kim; Koushik K. Das; Rajiv V. Joshi; Ching-te Chuang;
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年度 2013
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专利

1. Leakage Power Analysis of 25-nm Double-Gate CMOS Devices and Circuits [J] . Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, IEEE Transactions on Electron Devices . 2005,第5期

机译：25nm双栅极CMOS器件和电路的泄漏功率分析
2. Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit [J] . Deeprose Subedi, Eugene John International Journal of VLSI Design & Communication Systems . 2012,第5期

机译：使用自调节电压电平电路的纳米级静态CMOS VLSI乘法器电路的待机泄漏功率降低
3. Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power [J] . P.Prashanti, A.Shravya, K.Dhruthi Vasista, International Journal of Engineering Trends and Technology . 2017,第6期

机译：纳米CMOS VLSI系统的漏电降低技术及技术扩展对漏电功率的影响
4. Nanoscale CMOS circuit leakage power reduction by double-gate device [C] . Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Low Power Electronics and Design, 2004. ISLPED '04 . 2004

机译：双栅器件降低纳米CMOS电路泄漏功率
5. Performance tradeoff of leakage reduction techniques in nanoscale CMOS circuits. [D] . Koppa Venkataswamy, Santosh Kumar. 2009

机译：纳米级CMOS电路中减少泄漏技术的性能折衷。
6. Characteristic Fluctuations of Dynamic Power Delay Induced by Random Nanosized Titanium Nitride Grains and the Aspect Ratio Effect of Gate-All-Around Nanowire CMOS Devices and Circuits [O] . Yiming Li, Chieh-Yang Chen, Min-Hui Chuang, 2019

机译：随机纳米氮化钛晶粒引起的动态功率延迟的特性波动以及全能门纳米线CMOS器件和电路的纵横比效应
7. Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits [O] . Paulo F. Butzen, Leomar S. da Rosa, Erasmo J.D. Chiappetta Filho, 2010

机译：通过在纳米级CMOS数字电路中交互漏电流机制来备用功耗估计

3.3 Nanoscale CMOS Circuit Leakage Power Reduction by Double-Gate Device

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