Validating the Itanium 2 Exception Control Unit: A Unit-Level Approach

摘要

Each new microprocessor endeavor strives to achieve the performance gains projected by Moore's law. Such performance arises, in part, from innovative and often from complex microarchitectural features. The Pentium family has achieved impressive performance through aggressive out-of-order instruction execution, delicately balancing features such as instruction replay, register allocation, and exception resolution. The Pentium 4 was the first Intel processor to introduce hardware support for multithreading, where each thread executes on a private copy of architectural state. Future processor directions include moving from multiple active contexts to multiple processing cores on a single die. This trend of increasing functional complexity has already exacerbated the challenge of design validation, making validation the critical path to tapeout. Traditional approaches to functional validation include both focused case writing and the development of randomcode generators. Focused case writing usually develops from existing test coverage analysis or detailed examination of machine structures and protocols. In either case, this method is limited to engineering "thought" experiments—the human mind can only process a finite set of states in a seemingly infinite machine state space. Such an argument is the motivation behind random-code generators, which relieve verification engineers of having to preconceive every important corner case. These tools stress the machine with a random pattern of instructions and events, and are tunable via probability files to target specific machine behavior. The generators, however, usually operate at the full-chip level and can have difficulty hitting convoluted cases deep within the machine hierarchy. Other approaches have included adapting the full-chip cases to a unit-level environment to divide and conquer the verification task.