New Method for Evaluating Electric Field at Junctions of DRAM Cell Transistors by Measuring Junction Leakage Current

摘要

A new method for the analysis of dynamic random-access memory (DRAM) data-retention characteristics is developed. We extend a 1-D model of the bias dependence of the electric field in a p-n junction in DRAM to a 2-D model. The validity of the new model is confirmed by simulations and experiments. We then find that the electric-field strength in DRAM can be easily evaluated by measuring the substrate-bias dependence of the off-state leakage current of DRAM by using a test element group. The simulated electric-field strength does not always correspond to actual situations, so our method is very useful to monitor the electric-field strength in an actual device. Furthermore, we experimentally confirm that the electric field in DRAM strongly affects the tail-$t_{rm ret}$, which is the worst case of the retention-time distribution. We confirmed that the relationship between the tail- $t_{rm ret}$ and the electric-field strength in DRAM is constant even if gate length changes. On the other hand, we confirmed that the tail-$t_{ rm ret}$ becomes lower with an increasing number of defects around the p-n junction in DRAM even if the electric-field strength does not change. At the development stage, comparing data of electric-field strength and tail-$t_{rm ret}$ measured in preproduction samples to those in previous products, we can determine which method is more effective to increase tail- $t_{rm ret}$:lowering the electric-field strength or reducing the number of defects in devices. Our method for evaluating an electric field is applicable to all generations of DRAM, so it will be a powerful tool f-n-nor the design of DRAMs with an adequate retention time.