首页> 外国专利> / DRAM device memory cell transistor having source/drain junction region of different junction profile connected DC node and BC node and manufacturing method thereof

/ DRAM device memory cell transistor having source/drain junction region of different junction profile connected DC node and BC node and manufacturing method thereof

机译:于dc节点和bc节点连接有不同结轮廓的源/漏结区的dram装置存储单元晶体管及其制造方法

摘要

PURPOSE: A memory cell transistor of a DRAM(Dynamic Random Access Memory) device having source/drain junction region of different junction profile connected to DC node and BC node, and manufacturing method thereof are provided to be capable of improving static and dynamic refresh characteristics. CONSTITUTION: A memory cell transistor is provided with a gate stack pattern(60) formed at the upper portion of a semiconductor substrate(50), a DC and BC node formed at both sides of the gate stack pattern on the surface of the semiconductor substrate for being electrically connected with a bit line and a capacitor storage node, and a source/drain region(72a,72b) having a different junction profile, formed in the semiconductor substrate.
机译:用途:具有不同结轮廓的源极/漏极结区连接到DC节点和BC节点的DRAM(动态随机存取存储器)设备的存储单元晶体管及其制造方法,其能够改善静态和动态刷新特性。组成:一个存储单元晶体管在半导体衬底(50)的上部形成有栅叠层图案(60),在半导体衬底表面上的栅叠层图案的两侧形成有DC和BC节点在半导体衬底中形成有用于与位线和电容器存储节点电连接的晶体管,以及具有不同结轮廓的源/漏区(72a,72b)。

著录项

  • 公开/公告号KR20030085897A

    专利类型

  • 公开/公告日2003-11-07

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号KR20020024198

  • 发明设计人 AHN SU JIN;

    申请日2002-05-02

  • 分类号H01L27/108;

  • 国家 KR

  • 入库时间 2022-08-21 23:45:54

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号