Low resistivity contact methodologies for silicon, silicon germanium and silicon carbon source/drain junctions of nanoscale CMOS integrated circuits.

摘要

State-of-the-art p-channel metal oxide semiconductor field effect transistors (MOSFETs) employ Si1--xGe x source/drain junctions to induce uniaxial compressive strain in the channel region in order to achieve hole mobility enhancement. It is also known that the electron mobility can be enhanced if the MOSFET channel is under uniaxial tension, which can be realized by replacing Si1-- xGex with Si 1--yCy epitaxial layers in recessed source/drain regions of n-channel MOSFETs.;This dissertation focuses on epitaxy of Si1-- yCy layers and low resistivity contacts on Si, Si1--xGe x, and Si1--yC y alloys. While these contacts are of particular importance for future MOSFETs, other devices based on these semiconductors can also benefit from the results.;The experimental work on Si1--yC y epitaxy focused on understanding the impact of various process parameters on carbon incorporation, substitutionality, growth rate, phosphorus incorporation and activation in order to achieve low resistivity Si1-- yCy films with high substitutional carbon levels. It was shown, for the first time, that phosphorus levels above 1021 cm-3 can be achieved with 1.2% fully substitutional carbon in epitaxial layers.;Specific contact resistivity (rhoc) on strained Si 1--xGex layers was evaluated based on published results from band structure calculations. Previous work on this topic mainly focused on barrier height and the doping density at the interface. In this work, the impact of tunneling effective mass on specific contact resistivity was calculated for the first time for strained Si1--xGe x alloys. It was shown that due to the exponential dependence of contact resistivity on tunneling effective mass, it may have a strong impact on source/drain contact resistivity. This is especially important for strained alloys in which the tunneling effective mass is dependent on the strain. The contact resistivity was found to decrease with Ge concentration due to the smaller tunneling effective mass in strained Si1-- xGex. These calculations can also be extended to Si1--yC y junctions when better models for the Si1-- yCy band structure are available.;Two different metallization schemes were considered to achieve low resistivity contacts. In the first approach, two band edge silicides were used to achieve low-resistivity contacts for complimentary MOSFETs. For this purpose, experiments were conducted on band edge silicides including PtSiGe, NiSiC and ErSiC. The impact of Ge and C on silicide formation and the barrier height at the interface was investigated. Barrier height values around 0.3 eV were achieved with PtSiGe and ErSiC contacts formed on p-Si1--xGe x and n-Si1--yC y, respectively. Due to the exponential dependence of contact resistivity on barrier height, this barrier height is low enough to yield contact resistivity figures below 10-8 O-cm 2 even with modest doping levels. On the other hand, smaller barrier height values will be needed for Schottky barrier MOSFETs.;It is more desirable to use a single metal contact on both p- and n-channel MOSFETs, which requires tuning of the barrier height. Impurity implantation was considered as a means to achieve barrier height tuning. Extremely small barrier height values (≤ 0.1 eV) were obtained by sulfur segregation for the silicides of Pt, Ni and NiPt on n-type Si and Si1-- yCy. Indium segregation was used for the first time to lower the hole barrier height to obtain barrier height values below 0.2 eV on p-Si.;Interfacial segregation of platinum (Pt) was investigated at NiSi/Si and NiSi1--zCz/Si 1--yCy junctions to modulate the Schottky barrier height. It was demonstrated that the barrier height of NiSi/p-Si can be lowered below 0.2 eV, while that of NiSi1-zCz/p-Si1--yC y is preserved. The fact that the presence of carbon retards the barrier height modulation by interfacial segregation provides a lithography free process to tune the hole barrier height. This process can be a complementary process to the electron barrier height tuning by sulfur segregation.;The results provide several approaches that can be used to form low resistivity contacts. We believe that the knowledge gained from this work is expected to have a significant impact on choosing the most effective and economical approach to form low-resistivity contacts in CMOS manufacturing.