In-situ doped silicon germanium and silicon carbide source drain region for strained silicon CMOS transistors

摘要

A method for forming a semiconductor integrated circuit device, e.g., MOS, CMOS. The method includes providing a semiconductor substrate, e.g., silicon substrate, silicon on insulator. The method includes forming a dielectric layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the semiconductor substrate. The method also includes forming a gate layer (e.g., polysilicon) overlying the dielectric layer. The method patterns the gate layer to form a gate structure including edges. The method includes forming a dielectric layer overlying the gate structure to protect the gate structure including the edges. In a specific embodiment, sidewall spacers are formed using portions of the dielectric layer. The method etches a source region and a drain region adjacent to the gate structure using the dielectric layer as a protective layer. In a preferred embodiment, the method deposits using selective epi growth of silicon germanium material into the source region and the drain region to fill the etched source region and the etched drain region and simultaneously introduces a dopant impurity species into the silicon germanium material during a portion of the time associated with the depositing of the silicon germanium material to dope the silicon germanium material during the portion of the time associated with the depositing of the silicon germanium material. In a specific embodiment, the method also includes causing a channel region between the source region and the drain region to be strained in compressive mode from at least the silicon germanium material formed in the source region and the drain region.