Corrections to “Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications”

Yamada T.; Nakajima Y.; Hanajiri T.; Sugano T.

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Corrections to “Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications”

机译：对“通过低功率电源片上系统应用的源/漏工程抑制绝缘硅上MOSFET的漏极感应势垒降低的修正”

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来源
《IEEE Transactions on Electron Devices》 |2013年第12期|4281-4283|共3页
作者
Yamada T.; Nakajima Y.; Hanajiri T.; Sugano T.;
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作者单位

Bio-Nano Electronics Research Centre, Toyo University, Kawagoe, Japan|c|;

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收录信息美国《科学引文索引》(SCI);美国《工程索引》(EI);
原文格式 PDF
正文语种 eng
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1. Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications [J] . Yamada T., Nakajima Y., Hanajiri T., Electron Devices, IEEE Transactions on . 2013,第1期

机译：通过低功耗电源片上系统的源极/漏极工程，抑制绝缘体上硅MOSFET中的漏极感应势垒降低
2. Suppression of drain-induced barrier lowering by double-recess overlapped gate structure in normally-off AIGaN-GaN MOSFETs [J] . Sato Taku, Uryu Kazuya, Okayasu Junichi, Applied Physics Letters . 2018,第6期

机译：常关型AIGaN-GaN MOSFET中双凹槽重叠栅极结构抑制漏极感应势垒降低
3. Source-Drain Junction Engineering Schottky Barrier MOSFETs and their Mixed Mode Application [J] . Silicon . 2020,第4期

机译：源 - 漏极结合工程肖特基屏障MOSFET及其混合模式应用
4. Analytic Compact Model of Ballistic and Quasi-ballistic Cylindrical Gate-All-Around MOSFET Incorporating Drain-Induced Barrier Lowering Effect [C] . He Cheng, Shigeyasu Uno, Kazuo Nakazato Annual NSTI nanotechnology conference and expo;TechConnect world innovation conference expo . 2014

机译：包含漏极诱导势垒降低效应的弹道和准弹道圆柱形全能MOSFET的解析紧凑模型
5. Gate and source/drain engineering for nanoscale MOSFET applications. [D] . Yuan, Jun. 2005

机译：用于纳米级MOSFET应用的栅极和源极/漏极工程。
6. Drain Current Modulation of a Single Drain MOSFET by Lorentz Force for Magnetic Sensing Application [O] . Prasenjit Chatterjee, Hwang-Cherng Chow, Wu-Shiung Feng 2016

机译：洛仑兹力对单漏极MOSFET的漏极电流调制用于磁传感应用
7. Impact of Energy Relaxation of Channel Electrons on Drain-Induced Barrier Lowering in Nano-Scale Si-Based MOSFETs [O] . Ling-Feng Mao 2017

机译：信道电子能量松弛对纳米Si基MOSFET中排水管屏障降低的影响
8. Avalanche-Induced Drain-Source Breakdown in Silicon-on-Insulator n-MOSFET's [R] . Young, K. K., Burns, J. A. 1988

机译：绝缘体上硅n-mOsFET中的雪崩引起的漏源击穿

Corrections to “Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications”

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