Gate and source/drain engineering for nanoscale MOSFET applications.

摘要

Metal gates are expected to replace polysilicon gates in nanoscale MOSFETs. Full nickel silicidation of polysilicon gates is very promising for its process compatibility and for many other reasons. The work function of nickel silicide has been investigated, and a mid-gap work function value of 4.7eV was obtained for the undoped nickel mono-silicide (NiSi). Implantation of either arsenic or antimony into the polysilicon before silicidation can shift the NiSi work function towards the conduction band, while indium implantation can shift it towards the valence band. The physical mechanism responsible for this work function shift is the species pile-up at the oxide interface during the nickel silicidation process. Thus, dual work function metal gates can be obtained for NMOS and PMOS respectively by using a single full silicidation gate process. Silicidation conditions and species activation temperatures before silicidation were also found to have a significant effect on the work function shift.; Split-gate engineering has been studied for improving both the transconductance and the output resistance down to the nanoscale regime for MOSFET RF/Analog applications. The properly designed split gate HL device (H: high work function gate electrode close to the source; L: low work function gate electrode close to the drain) can enhance source carrier injection into the channel and increase the output resistance together, thus improving frequency-gain performance. NiSi split gates have been achieved by doping polysilicon gates locally with antimony or indium before gate full silicidation process, since the work functions are different for the NiSi gate regions with/without dopants under them. Improved current drive capability and output resistance have been observed in the NiSi split gate MOSFETs. The gate oxide was not degraded due to the low temperature silicidation process, and no poly-depletion-effects were observed in the NiSi gates. The second method, spacer gate engineering with gate partial silicidation, has been utilized to form a polysilicon/CoSi2 split gate. A split gate with a ∼0.15 mum length has been demonstrated.; Source/drain optimization in sub-50nm bulk and double-gate MOSFET have been studied by using TCAD tools. (Abstract shortened by UMI.)