Complementary MOS logic circuit has inverter with two MOSFETs - in drain-drain series and depleted types gate connected to its source

摘要

The complementary MOS logic circuit has an inverter which is constructed from two complementary MOSFETs which are connected together at their drains to a common output terminal (3) and are connected by their sources to the oppositely-poled supply terminals (4, 6). The input signal (5) is applied to the MOSFET at the first gate. The second MOSFET (2) is depleted and has its gate connected to its source. The advantage of the logic lies in its avoiding delays arising from capacitance when connected into a chain of logic elements. The logic also has increased packing density.