A Double-Spacer I-MOS Transistor With Shallow Source Junction and Lightly Doped Drain for Reduced Operating Voltage and Enhanced Device Performance

摘要

In this letter, a double-spacer (DS) design is utilized for the formation of shallow source and lightly doped drain to further optimize the impact-ionization MOS (I-MOS) transistor structure. The breakdown voltage $V_{{bf BD}}$ needed for avalanche breakdown is lowered due to the shallow source extension. With the formation of the lightly doped drain extension, the impact of drain bias on breakdown voltage, and hence, the threshold voltage $V_T$ is also reduced. The DS I-MOS is fabricated and characterized. Detailed analysis and physical explanation of the impact of drain/gate bias on the device characteristics are provided. Compared to the conventional I-MOS transistor, the shallow source extension reduces the breakdown voltage [drain-induced breakdown voltage lowering (DIBVL)] by 0.3–0.6 V, and the lightly doped drain extension reduces the DIBVL up to 0.17 V/V. In addition, excellent subthreshold swing and good device performance are achieved.