A Novel Five-Photo-Mask Low-Temperature Polycrystalline-Silicon CMOS Structure With Improved Contact Resistance

摘要

In this letter, a novel five-mask low-temperature polycrystalline-silicon (LTPS) complementary metal–oxide–semiconductor (CMOS) structure was proposed to improve cost competitiveness of CMOS products on the market and was verified by manufacturing test samples using the five-mask LTPS CMOS process. Selective contact-barrier-metal formation process was first introduced to solve the high-contact-resistance problem encountered between indium–tin-oxide and doped poly-Si source/drain. The five-mask CMOS devices showed comparable device performances to CMOS devices with conventional structure, i.e., 1.32 V of threshold voltage and 267.6 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ of maximum field-effect mobility for NMOS, and those of $-$1.24 V and 125.2 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$ for PMOS, respectively.