METHOD FOR FORMATION OF LOW-RESISTANCE CONTACTS IN SUBMICRON CMOS -STRUCTURES OF LARGE INTEGRAL CIRCUITS

摘要

A method for formation of low-resistance contacts in submicrone CMOS-structures of large integral circuits includes chemical treatment of silicon substrates, oxidation, formation by implantation of self-aligned drain-source regions, a gate insulator, a interlayer insulator, projection lithography and anisotropy plasma-chemical etching functional layers. After contacting windows opening and profiling thereof multiple-charge retrograde ion implantation of germanium with energy of 20-150 keV and doze of 0.1-50 Kl/cmis performed depending on depth of occurrence of p-n transients and concentration of highly-alloyed regions.