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首页> 外文期刊>Turkish Journal of Electrical Engineering and Computer Sciences >Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology
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Single event multiple upset-tolerant SRAM cell designs for nano-scale CMOS technology

机译:用于纳米级CMOS技术的单事件多重容错SRAM单元设计

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摘要

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75% lower PDP compared with DICE), much more soft error robustness, and larger noise margins.
机译:在本文中,提出并评估了两个软容错SRAM单元,即所谓的RATF1和RATF2。拟议中的辐射硬化SRAM单元能够完全容忍单事件不安定(SEU)。此外,它们显示出对单事件多次不安(SEMU)的高度鲁棒性。与之前的SRAM单元相比,RATF1和RATF2提供了较小的面积和功耗。通过将Hspice仿真结果与一些著名的先进的软容错SRAM单元进行比较,结果表明,我们提出的稳健SRAM单元具有较小的面积开销(RAFT1比DICE减小了58%的面积),更低的功率延迟乘积(RATF1)与DICE相比,它提供的PDP降低了231.33%,而RATF2的PDP降低了74.75%),软错误鲁棒性更高,噪声容限更大。

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