Source/drain engineering for extremely scaled MOSFETs.

摘要

As MOSFET feature sizes are scaled down to the deep sub-tenth micron regime, serious degradation of MOSFET device performance due to extrinsic elements, including parasitic resistance and capacitance, is one of the challenging issues for high performance, low voltage device design. In particular, careful source/drain (S/D) engineering is necessary for extremely scaled MOSFETs to maximize the intrinsic performance. In our work, high performance source/drain engineered MOSFETs structures are reported to match the requirements depicted in the International Technology Roadmap for Semiconductors (ITRS).; First, bulk MOSFETs design considerations with S/D engineered structure are presented with a Source/Drain on Insulator (SDOI) structure for high performance application with less parasitics. A self-align double spacer process to fabricate SDOI device is proposed and process feasibility is discussed. Design guideline and potential performance gain with the SDOI structure are also discussed. Secondly, design considerations with silicon-on-insulator (SOI) source/drain engineered structure are discussed and a Self-Align Recessed Source Drain (ReS/D) Ultra-Thin Body SOI MOSFETs is designed. The ReS/D structure provides more design flexibility with parasitic source/drain resistance and gate-to-drain miller capacitance. Fabrication details and experimental results are presented. The scalability of the ReS/D MOSFETs and the larger design window due to reduced parasitics are demonstrated. Finally, source/drain engineering structure with contact design schemes for doublegate (DG) technologies to enhance the current drive ability and to provide larger design flexibility are discussed. FinFET with side contact scheme shows more potential benefit over conventional top contact scheme to push the CMOS device scaling to its limit.