首页> 外国专利> Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance and contact resistance due to wrap-around structure of source/drain regions

Method for forming an extremely thin silicon-on-insulator (ETSOI) device having reduced parasitic capacitance and contact resistance due to wrap-around structure of source/drain regions

机译:形成极薄的绝缘体上硅(ETSOI)器件的方法,该器件由于源极/漏极区的环绕结构而具有减小的寄生电容和接触电阻

摘要

A method for forming a semiconductor device includes etching a semiconductor layer using a gate structure and spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure. Undercuts are formed in a buried dielectric layer under the gate structure. Source and drain regions are epitaxially growing and wrapped around the semiconductor layer by forming the source and drain regions adjacent to the gate structure on a first side of the semiconductor layer and in the undercuts on a second side of the semiconductor layer opposite the first side.
机译:用于形成半导体器件的方法包括:使用栅极结构和间隔物作为掩模来蚀刻半导体层,以保护半导体层的延伸超出栅极结构的部分。在栅极结构下方的掩埋电介质层中形成底切。通过在半导体层的第一侧上以及在与第一侧相对的半导体层的第二侧上的底切中形成与栅极结构相邻的源极和漏极区域,来外延生长源极和漏极区域并围绕半导体层缠绕。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号