Reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions

摘要

A semiconductor device includes a buried dielectric layer and a semiconductor layer provided on the buried dielectric layer. A gate structure is formed on the semiconductor layer and has portions of the semiconductor layer extending beyond the gate structure. Source and drain regions are wrapped around ends of the semiconductor layer such that a first portion of the source and drain regions is formed on a first side of the semiconductor layer adjacent to the gate structure, and a second portion of the source and drain regions is formed on a second side of the semiconductor layer opposite the first side.