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Impacts of wire-LER on Nanowire MOSFET devices, subthreshold SRAM and logic circuits

机译:线LER对Nanowire MOSFET器件,亚阈值SRAM和逻辑电路的影响

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摘要

We propose a methodology to simulate realistic 2D Line Edge Roughness (LER) pattern for NanoWire (NW) MOSFETs in TCAD platform. This approach predicts the device characteristic and variations including Vth, Ion and Subthreshold Swing (S.S.) fluctuations more accurately compared with prior literature considering two types of primarily 1D NW geometry variation [1]. Based on the proposed simulation approach, we carry out a comprehensive analysis using 3D atomistic TCAD and mixed-mode Monte Carlo simulations on the impacts of Wire-LER on the variability of NW MOSFET device characteristics, stability of 6T SRAM operating in subthreshold region and logic circuits. The results are extensively compared with previous approaches to illustrate the deficiency of modeling and predictions based on 1D NW geometry variation.
机译:我们提出了一种方法,可以在TCAD平台中模拟逼真的2D线边缘粗糙度(LER)模式用于NanoWire(NW)MOSFET。与现有文献相比,这种方法可以更准确地预测器件的特性和变化,包括Vth,离子和亚阈值摆幅(S.S.)波动,其中考虑了两种主要是一维NW几何变化的类型[1]。基于提出的仿真方法,我们使用3D原子TCAD和混合模式Monte Carlo仿真对Wire-LER对NW MOSFET器件特性的可变性,在阈值以下区域工作的6T SRAM的稳定性和逻辑的影响进行了综合分析电路。将结果与以前的方法进行了广泛比较,以说明基于1D NW几何变化的建模和预测的不足。

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