Process for integrating stacked capacitor DRAM devices with MOSFET devices used for high performance logic circuits

摘要

A semiconductor fabrication process has been developed in which both stacked capacitor DRAM, and MOSFET logic device structures, are integrated on a single silicon chip. The process features combining process steps for both device types. A single dielectric layer is used as a capacitor dielectric layer, for a stacked capacitor DRAM device, and as a gate insulator layer for a MOSFET logic device. In addition a specific polysilicon layer is used for formation of the upper polysilicon electrode, for the stacked capacitor DRAM device, as well as use for formation of the polysilicon gate structure, for the MOSFET logic device. A specific anneal cycle is used to reduce charges in the stacked capacitor DRAM device, while a less severe anneal cycle is used with the shallow junction MOSFET logic device.