Proven Practice and Future Application of POlysilicon CMP in IC Fabrication

摘要

This paper reviews and reports advancements in polysilicon CMP development for five different applications in IC fabrication. The most noticeable one is polysilicon plug CMP for DRAM applications. The second is polysilicon gate CMP. The third is dual salicide and self-aligned metal gate (SAMG) formation. The fourth is deep/shallow trench polysilicon CMP for isolation applications. The fifth is sacrificial emitter polysilicon CMP for BiCMOS application. A polysilicon plug CMP process has been developed in Applied Materials' application lab and proven at a customer's DRAM fab on a MIRRA~circleR CMP equipment. A low within wafer non-uniformity (WIWNU, 2.7percent 1 sigma at 49 points and 5mm edge exclusion) has been achieved using a best-known-method (BKM) with a stable removal rate of 3625 A/min. The removal rate can be adjusted in the range of 3000 to 6000 A/min. without adverse impact on the WIWNU by changing slurry. The BKM consists of oxide breakthrough polish prior to polysilicon main polish followed by polysilicon overpolish. A robust process assisted by reliable endpoint detection has been developed for polysilicon CMP. A new pre-cleaning process including buffing and the surface conversion (from hydrophobic to hydrophilic) has also been developed as a post CMP step of the BKM to achieve a low defect level (25 counts at 0.16u for 8" wafer on Tencor 6200). The polysilicon CMP process is applicable to the polysilicon gate formation. The MIRRA~circleR platform has demonstrated to be the tool of choice for other emerging polysilicon CMP applications (such as dual salicide and self-aligned metal gate formation, deep/shallow trench isolation, and BiCMOS emitter formation) by meeting application requirements.