A novel bi-directional high voltage PMOS with trench gate structure (Waveform Depletion MOS: WDMOS) for 65V HVICs

摘要

In this paper, we propose a new bi-directional high voltage PMOSFET that improves a back-gate bias effect due to WDMOS (Waveform Depletion MOS) structure. In WDMOS structure, plural trench gates are adjacent each other. Therefore, the silicon between trench gates is easily depleted and a back-gate bias effect can be suppressed. We present excellent characteristics of the bi-directional high voltage PMOSFET with WDMOS structure.