A multi-chip packaged GaAs 16×16 bit parallel multiplier

摘要

A GaAs 16×16 16-bit parallel multiplier utilizing multichippackaging technology is demonstrated. This multichip approach was takenin an effort to realize GaAs ULSIs with high yield and reliability,using multiple smaller scale integrated circuits. The device is composedof four GaAs 8×8-bit expandable parallel multipliers and amultichip package (MCP). The developed 8×8 multipliers consist of1097 enhancement/depletion DCFL (directly coupled FET logic) gates each,and have a 3.4 ns multiplication time. The developed MCP is composed offive layers of alumina ceramic which include 50 Ω striplines. Themultiplication time of this 16×16-bit multichip multiplier is 7.6ns, and the total production yield is 70%