VLSI architecture for a 16-bit Multiply-Accumulator (MAC) operating in multiplication time.

摘要

Multiply-Accumulate is an important and expensive operation. It is frequently used in Digital Signal Processing and video/graphics applications. As a result, any improvement in the delay for performing this operation can have a positive impact on clock speed, instruction time and processor performance. This thesis shows how the performance of a parallel multiplier is improved, and how the application of recent innovations in the parallel multiplier can be used to design Multiply-Accumulators. This application results in Mutiply-Accumulators that are as fast as multipliers of the same size.