As CMOS technology has moved to 28nm technology node and beyond, the bevel cleaning is imperative to enhance yield performance for the complex film stacks, the weak adhesion force between these films and the inherent stress of ultra thick dielectric film at bevel area could cause serious peeling defects, especially in PVD (Physical Vapor Deposition) processes. We observed the bevel related oxide peeling defect generated after contact glue layer deposition process. The big size oxide slice defect blocks the contact hole, leading to tungsten missing after contact CMP (chemical mechanical polishing) and serious yield loss. Another bevel related defect was captured at far back-end. The 1st passivation oxide film could not survive the aluminum PVD process and peel off at bevel area. The defect size is on the order of several microns. This tends to result in Al photo defocus, Al pad bridge issue and CPI (chip package interaction) issue. In this course, we come up with several bevel etch schemes to improve the film status at bevel area for peeling defect reduction. We focused on the choice of bevel cleaning insert position(s), the optimization of recipe selectivity and the systemic integration scheme. An appropriate insert position is the preconditon of effective defect reduction. The high selectivity could also avoid the serious prelayer damage and extra defect resource generation.
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