首页> 外文会议>Microelectronic Manufacturing Yield, Reliability, and Failure Analysis >Process design for manufacturability of GaAs MESFET integrated circuit using statistical experimental design techniques
【24h】

Process design for manufacturability of GaAs MESFET integrated circuit using statistical experimental design techniques

机译:利用统计实验设计技术进行GaAs MESFET集成电路可制造性的工艺设计

获取原文

摘要

Abstract: A manufacturable, directly ion implanted 0.6 $mu@m GaAs metal- semiconductor field-effect transistors (MESFET) and metal-semiconductor- metal (MSM) based opto-electronic integrated circuit (OEIC) process has been developed and optimized for low cost optical data link applications. Key steps in the OEIC process have been identified and statistically quantifiable process modules have been obtained to optimize the circuit performance and achieve high process yield. The statistically significant transfer characteristics of each process module was obtained through design of experiment (DOE) and response surface modeling (RSM), by utilizing both experimental data and data from experimentally calibrated process simulators. This paper discusses the PECVD Si$-2$/N$-4$/ process module optimization and the backgating effects in GaAs ICs.!8
机译:摘要:已经开发了一种可制造的,直接离子注入的0.6μμmGaAs金属-半导体场效应晶体管(MESFET)和基于金属-半导体-金属(MSM)的光电集成电路(OEIC)工艺,并针对该工艺进行了优化。成本较高的光学数据链路应用。 OEIC工艺中的关键步骤已经确定,并获得了统计上可量化的工艺模块,以优化电路性能并实现高工艺良率。通过使用实验数据和来自经过实验校准的过程模拟器的数据,通过实验设计(DOE)和响应面建模(RSM)获得了每个过程模块的统计上显着的传递特性。本文讨论了PECVD Si $ -2 $ / N $ -4 $ /工艺模块的优化以及GaAs IC的背板效应!8

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号