LAYOUT DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AUTOMATIC LAYOUT DESIGN DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT, LAYOUT DESIGN ASSISTANCE SYSTEM OF SEMICONDUCTOR INTEGRATED CIRCUIT, PHOTOMASK, PHOTOMASK MANUFACTURING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD, CONTROL PROGRAM, AND READABLE STORAGE MEDIUM

摘要

PROBLEM TO BE SOLVED: To perform a freeze-silicon ECO so as to satisfy timing restrictions in the logic change of mask layout.;SOLUTION: A direction range of a spare cell to be replaced is detected by a spare cell direction range detection block 22, and a distance range satisfying timing restrictions is detected within the direction range by a timing restriction-satisfying range detection block 23. When no spare cell exists within the distance range satisfying the timing restrictions, an instance closest to a spare cell or a connection object is detected among used instances of the same kind as spare cells by a used replacement cell instance detection block 24, and both terminals of the detected instance are disconnected by a used replacement instance replacing block 25, and the instance is used instead of a spare cell. Disconnected terminal parts (unused circuit parts) are to be replaced to set a connection object again by a reference terminal coordinate resetting block 26, and each process is repeated one or a plurality of times.;COPYRIGHT: (C)2009,JPO&INPIT