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A new 600V partial SOI LDMOS with step-doped drift region

机译:具有阶跃掺杂漂移区的新型600V部分SOI LDMOS

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A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped profile induces an electric field peak in the surface of the device, which can improve the surface field distribution and the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance. The proposed LDMOS transistor with SDD in partial PSOI (SDD-PSOI) is analyzed by 2-D numerical simulations, compared with conventional SOI (CSOI) and conventional PSOI (CPSOI) LDMOS transistors. The results indicate that the proposed structure can significantly improve BV up to 607V and reduce on-resistance by 12.6% in comparison to CPSOI.
机译:引入了具有阶跃掺杂漂移区(SDD)的新型600V部分绝缘体上硅(PSOI)横向双扩散金属氧化物半导体(LDMOS)场效应晶体管,以改善击穿电压(BV)并降低导通电压。电阻(罗恩)。阶跃掺杂轮廓在器件表面感应出电场峰值,这可以改善表面场分布和漂移区中的掺杂容限。调整后的漂移区可以在漏极端下方允许更高的掺杂浓度,从而导致更高的击穿电压,并作为一个整体容纳更多的杂质原子,从而提供更多的电子来支持更高的电流,从而降低导通电阻。与传统的SOI(CSOI)和传统的PSOI(CPSOI)LDMOS晶体管相比,通过二维数值模拟分析了所提出的具有部分PSOI中的SDD的LDMOS晶体管(SDD-PSOI)。结果表明,与CPSOI相比,所提出的结构可将BV显着提高至607V,并将导通电阻降低12.6%。

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