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A new 600V partial SOI LDMOS with step-doped drift region

机译:具有阶梯式漂移区的新的600V部分SOI LDMOS

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A new 600V Partial Silicon-on-Insulator (PSOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect transistor with step-doped drift region (SDD) is introduced to improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped profile induces an electric field peak in the surface of the device, which can improve the surface field distribution and the doping accommodation in the drift region. The adjusted drift region can allow higher doping concentration under the drain end which results in higher breakdown voltage, and accommodate more impurity atoms as a whole which provides more electrons to support higher current and thus reduce on-resistance. The proposed LDMOS transistor with SDD in partial PSOI (SDD-PSOI) is analyzed by 2-D numerical simulations, compared with conventional SOI (CSOI) and conventional PSOI (CPSOI) LDMOS transistors. The results indicate that the proposed structure can significantly improve BV up to 607V and reduce on-resistance by 12.6% in comparison to CPSOI.
机译:引入新的600V部分硅环 - 绝缘体(PSOI)横向双扩散金属氧化物半导体(LDMOS)场效应晶体管,具有阶梯掺杂漂移区(SDD),以改善击穿电压(BV)并减少 - 抵抗(ron)。阶梯掺杂的轮廓在装置的表面中引起电场峰值,这可以改善漂移区域中的表面场分布和掺杂容纳。调节的漂移区域可以允许在漏极端下较高的掺杂浓度,这导致较高的击穿电压,并容纳更多的杂质原子作为整体,这提供了更多的电子以支持更高电流,从而降低导通电阻。通过2-D数值模拟分析了具有部分PSOI(SDD-PSOI)中的具有SDD的所提出的LDMOS晶体管,与常规SOI(CSOI)和传统的PSOI(CPSOI)LDMOS晶体管进行比较。结果表明,与CPSOI相比,所提出的结构可显着改善高达607V,降低12.6%的耐抗性。

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