INTERPOSER FOR 2.5D PACKAGING ARCHITECTURE

摘要

A chip package comprising: a chip, a substrate, an interposer module comprising a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the area of the first layer, whereby an exposed surface area of the first layer is generated, via openings extending at least partially through the first layer, via openings extending at least partially through the first layer and the second layer, a plurality of conductive routings, electrically coupled between the via openings,wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer, and an electronic component electrically coupled to the via openings of the exposed surface region of the first layer.