Fabrication methods and integrated circuit having a strained semiconductor CMOS transistor having a source and drain regions of the lattice mismatch

摘要

Topic There are times when the integrated circuit which possesses the p type field-effect transistor (PFET) and the n type field-effect transistor (NFET) is offered.Solutions As for the 1st distortion, it is not NFET and through the source only of PFET and the lattice unconformity semiconductor layer of the silicon which are arranged inside the drain territory & the germanium etc which, is not NFET and it is added to the channel territory of PFET. The process which forms PFET and NFET is offered. In order to add the distortion to the channel territory of PFET where the trench is etched in the source of PFET, and inside the area because it becomes the drain territory adjoins to that, epitaxial it grows lattice unconformity silicon & germanium layer there. It grows the layer of silicon with respect to silicon & germanium layer, forms silicate from layer of silicon, low the resistant source and it is possible to offer the drain territory. Selective figure Figure 1