Influence of asymmetric/symmetric source/drain region on asymmetry and mismatch of CMOSFET's and circuit performance

摘要

Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5-/spl mu/m surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated with four ion-implantation methods and designed with a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry in MOSFETs with a one-sided 7/spl deg/-implantation method. The symmetric 7/spl deg//spl times/4-implantation method gives good A&M characteristics of n- and p-MOSFET's with the both layouts. According to the circuit performance of ring oscillators, the ion-implantation method is correlated to supply-current/oscillation-frequency/delay-power product and substrate current. The symmetric 7/spl deg//spl times/4-implantation method is the most preferable in terms of A&M and punchthrough immunity of CMOSFET as well as circuit performance.