首页> 外国专利> PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER AND METHOD OF FABRICATING THE SAME

PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER AND METHOD OF FABRICATING THE SAME

机译:具有通过插件插入的包装基质及其制造方法

摘要

The invention provides a package substrate having a via hole medium layer embedded therein and a method of forming same, the substrate comprising a mold-sealing layer, a via hole medium layer formed with conductive via holes and embedded into the mold-sealing layer, a circuit re-distribution layer embedded in the mold-sealing layer and disposed on the via hole medium layer and electrically connected to either end surfaces of the conductive via holes, and a build-up layer disposed on the mold-sealing layer and the via hole medium layer and electrically connected to the other end surfaces of the conductive via holes. By embedding the via hole medium layer, the circuit redistribution layer can be electrically connected to electrode pads having smaller spacing therebetween that are formed on a semiconductor chip, while another end is connected to conductive blind via holes having larger spacing therebetween that are formed on the build-up layer, thereby allowing the package substrate to bond with the semiconductor chip having high density wiring formed thereon. The invention further provides a method for forming the package substrate as described above.
机译:本发明提供了一种封装基板,其具有嵌入其中的通孔介质层及其形成方法,该基板包括模具密封层,形成有导电通孔并嵌入到模具密封层中的通孔介质层,嵌入在密封层中并设置在通孔介质层上并电连接到导电通孔的任一端面的电路再分布层,以及设置在密封层和通孔上的积层介质层并电连接到导电通孔的另一端面。通过嵌入通孔介质层,电路再分配层可以电连接到在半导体芯片上形成的其间具有较小间距的电极焊盘,而另一端连接到形成在半导体芯片上的其间具有较大间距的导电盲孔。积层,从而允许封装基板与在其上形成有高密度布线的半导体芯片结合。本发明还提供一种用于形成如上所述的封装基板的方法。

著录项

  • 公开/公告号KR101414057B1

    专利类型

  • 公开/公告日2014-07-02

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20120098720

  • 发明设计人 청 췌이-장;후 디-충;

    申请日2012-09-06

  • 分类号H01L23/48;

  • 国家 KR

  • 入库时间 2022-08-21 15:40:39

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