As the minimum feature sizes of current integrated circuits approach 10 nm, improvementsudin the speed, complexity and packing density are becoming increasingly difficult. In particular,udat these scale, the operation of `classical' complementary metal-oxide-semiconductorud(CMOS) devices is expected to degrade unacceptably. Single-electron devices, where theudCoulomb blockade effect can be used to control charge at the one electron level, provideuda means to fabricate large scale integration (LSI) circuits with ultra-low power consumption,udimmunity from charge fluctuations, and high scalability at sub-10 nm dimensions.udSingle-electron devices are potentially a successor technology to conventional classical Siudmetal-oxide-semiconductor field effect transistors (MOSFETs), and will play an increasinglyudimportant role both in future CMOS and `beyond CMOS' technologies.udIn this thesis, we first introduce the history of single-electron (SE) effects and the previousudwork in both theory and practical fabrication. Subsequently, the theoretical operationudof the single-electron transistor (SET) is discussed, followed by a brief introduction to theudquantum dot (QD) and the multiple tunnel junction (MTJ) transistor. The fabricationudprocess for SET devices in heavily doped, n-type silicon-on-insulator (SOI) material, usingudthe electron-beam lithography (EBL), is then introduced. Two types of Si SET devicesudhave been studied, the 1 μm nanowire (NW) SET and `point gate' SET, which are bothuddefined by EBL followed by reactive-ion etching (RIE) to create trench isolation of theuddevices, source, drain and nanowire regions. A thermal oxidation approach, was then usedudto reduce the Si core to the sub-10 nm scale in the NW. This passivates surface defects,udcreates charging 'islands' isolated by tunnel barriers and forms the SET. Variation in surfaceudroughness, doping concentration and any disorder inherent at the nanoscale can formudthe tunnel barriers con ning the charging island. The SiNW SETs fabricated in this workudhave been electrically characterised at temperatures from 8 - 300 K. Results obtained from NWs with core widths from 5 nm to 40 nm with two di erent gate lengths of 1 μmudto 50 nm have been compared. Here, detailed Ids vs. Vds, Vgs measurements have beenudperformed at 8 K, and `Coulomb diamond' characteristics have been observed. The 1 μmudlong NWs behave as MTJs, with 40 nm scale islands. Here, the width of the Coulombuddiamond cannot be reduced to zero. The detailed temperature dependence of the Ids vs.udVds characteristics show that some SE effects persist even at 300 K. The reduction inudNW gate length to 50 nm reduces the likelihood of quantum dots to only three dots, butudincreases their influence on the electrical characteristics. In the point contact device, QDudbehaviour with a combination of SE charging and quantum confinement effects is observedudat 8 K. In a highly scaled point circuit Coulomb blockade and a single-electron oscillationudare observed. Monte Carlo simulations have been used to further investigate the devicesudand their island con gurations. The results of this thesis demonstrate explicitly the signicance of quantum effects for the electrical performance of nominally `classical' SiNWuddevices and highlight their potential for quantum effect `beyond CMOS' devices.
展开▼
