Fabrication and Characterization of High Performance Silicon Nanowire Field Effect Transistors.

摘要

Quasi one-dimensional (1-D) field-effect transistors (FET), such as Si nanowire FETs (Si NW-FETs), have shown promise for more aggressive channel length scaling, better electrostatic gate control, higher integration densities and low-power applications. At the same time, an accurate bench-marking of their performance remains a challenging task due to difficulties in definition of the exact channel length, gate capacitance and transconductance. In 1-D Si FETs, one also often observes a significant degradation of their mobility and on/off ratio. The goal of this study is to implement the idea of the FET performance enhancement while simultaneously performing a more rigorous data extraction. To achieve these goals, we fabricated dual-gate undoped Si NW-FETs with various NW diameters The Si NWs are grown by Au-catalyzed vapor-transport For our top-gate NW-FET, the subthreshold swing was determined to be 85-90 mV/decade, whereas the best subthreshold swings for Si NW-FETs until now were ∼135-140 mV/decade. We achieved a ON/OFF current ratio of 107 due to improved electrostatic control and electron transport conditions inside the channel. This is on the higher end of any ON/OFF ratios thus far reported for NW FETs The hole mobility in our NW-FETs was around 250.400 cm2/Vs, according to different extraction procedures. In our mobility calculations we included the NW silicidation effect, which reduces the effective channel length. We calculated the top gate capacitance using Technology Computer Aided Design (TCAD) Sentaurus simulator, which gives more accurate value of capacitance of the NW over any analytical formulas. Thus we fabricate and rigorously study Si NW.s intrinsic properties which are very important for digital logic circuit application. In the second part of the study, we carried out simulation of Si NW FET devices to shed light on the carrier transport behavior that also explains experimental data.