Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs

摘要

Semiconductor devices with a low gate leakage current are preferred for lowudpower application. As the devices are scaled down, sidewall spacer for CMOS transistorudin nano-domain becomes increasingly critical and plays an important role in deviceudperformance evaluation. In this work, gate tunneling currents have been modeled for audnano-scale MOSFET having different high-k dielectric spacer such as SiO₂, Si₃N₄,udAl₂O₃, HfO₂. The proposed model is compared and contrasted with Santaurus simulationudresults and reported experimental result to verify the accuracy of the model. Theudagreement found was good, thus validating the developed analytical model. It is observedudin the results that gate leakage current decreases with the increase of dielectric constantudof the device spacer. Further, it is also reported that the spacer materials impact theudthreshold voltage, on current, off current, drain induced barrier lowering and subthresholdudslope of the device.